Analog-to-digital conversion algorithms implemented in silicon (successive approximation registers or SARs, switched-capacitor and switched-current pipelines, folding, flash, etc.) inherently rely on the precision, accuracy, stability, and low noise of some internal reference voltage signal against which the input signals must be weighted. In particular, switched-capacitor implementations draw current out of the reference lines to charge/discharge the capacitors employed for processing the signal (in each stage's Multiplicative Digital-to-Analog Converter, or MDAC), usually perturbing the reference signal more than in switched-current implementations. For instance, the flash sub-ADC found in the first stage of a switched-capacitor pipeline conversion chain measures the signal against a resistor (or capacitor) ladder, setting the comparator thresholds. Consequently, any error and/or noise affecting the voltage references directly impacts the performance of the whole ADC, without any possibility left for correction unless some form of time-consuming and background calibration is employed.
One prior art circuit solution to the problem of Vref modulation from MDAC capacitors in a switched-capacitor pipelined ADC is shown in FIG. 1. Essentially, the solution is to attenuate the charge injection of the DACs that couples into the rectifying, very low-speed high-precision Vref regulation loop. Circuit 100 includes an amplifier 102 having a positive input for receiving the VIN input voltage, a negative input, and an output. The regulation loop 104 includes a triple-Darlington transistor circuit including bipolar transistors Q1, Q2, and Q3 coupled to corresponding resistors R1, R2, and R3. The loop is stabilized as is known in the art with compensation capacitor CLOOP. The circuit “driver”, 106 comprising transistors Q4, Q5, and Q6 coupled to corresponding resistors R4, R5, and R6, is a scaled replica of the triple- (or more in general, multiple-) Darlington connection of transistors Q1 through Q3 and resistors R1 through R3 found inside the regulation loop. Thus, by way of example, transistors Q3 and Q6 maintain the same relative current and voltage bias conditions such that a precisely regulated voltage is produced at the emitter of transistor Q3 and replicated at the emitter of transistor Q6 (VREF).
The series of instantaneous charge packets drawn by the switched-capacitors within the MDAC circuitry 108 (MDAC in the case of an ADC) causes the Vref node to be affected in turn by a series of voltage pulses, which is not directly coupled into the loop. The pulses are attenuated by the gain of the replicated circuitry as represented by Q4 before being introduced back into the loop. At high frequency, the attenuation can be modeled by a capacitive ratio approximately equal to Cπ/CLOOP as determined by charge-sharing. The addition of further decoupling stages, such as followers, to both the replica and driver circuits increases the attenuation. The solution shown in FIG. 1 prevents the pulse train coming from the Vref output to be injected at full strength into the slow, precision loop 104 used to regulate Vref. The envelope of the pulse train (known to be modulated by the input signal of the ADC) could in fact be sensed by the slow reaction of the loop, and possibly be rectified and/or distorted by the intrinsic non-linearity of the devices in the loop. This would have the undesirable result of transforming a slow envelope modulation of the pulse train into a slow DC modulation of the Vref itself.
A second prior art circuit solution is shown in FIG. 2 that does not attenuate, but rather attempts to eliminate the voltage modulation inside the Vref loop. This is accomplished by coupling to a capacitor the voltage synthesized by the loop to produce the desired Vref at the circuit driver's output, and disconnecting the loop during the occurrence of the pulses on the MDAC. Thus, there are instants at which the capacitor alone drives the output buffer, whose gate is held to the correct voltage level by the capacitor. This solution is shown in circuit 200 of FIG. 2. Circuit 200 includes the well known linear regulator circuit 204 including an amplifier 202, transistor M1, resistor R1, and compensation capacitor CLOOP. The source of transistor M1, node 214, is designated VREF_LOOP. In addition, circuit 200 includes a replica driver stage 206 including transistor M2, resistor R2, and capacitor CISO for providing the VREF reference voltage to MDAC 208. The replica driver stage is coupled to the voltage regulator 204 through switch 216. A switch driver circuit 210 receives an input clock signal from inverter 212, and provides the synchronization signal to both switch 216, as well as to switching circuitry in MDAC 208. Circuit 200, in operation, decouples the sensitive loop in regulator 204 from the pulse train affecting the replica driver immediately before a pulse occurs, and reconnects the replica driver immediately after such pulse during the quiet phase of the MDAC cycle. The method of operation of circuit 200 substantially eliminates the undesirable Vref modulation of the ADC input signal.
However, the solution provided by circuit 200 of FIG. 2 presumes precise voltage matching between the regulator and replicated driver circuit. A portion of the regulator and a portion of the replicated driver circuit are shown as circuit 300 in FIG. 3. The regulator includes transistor M1, resistor R, and capacitor CLOOP, and is coupled to ground voltage VGND. The voltage at the gate of transistor M1 is VLOOP. The driver circuit includes transistor M2 (a factor of m larger than M1), resistor R/m, and capacitor CISO, and is coupled to ground voltage VGND′. The regulator circuit and the driver circuit are coupled through switch 316. The potential at the gate of transistor M1 is Vloop=VGS+R*I+VGND. For this voltage to produce the desired, precise effect in the replicated driver circuit, it is presumed to be matched by identical, or scaled, electrical quantities. However, the separate connection of the two ground voltages VGND and VGND′ forces a different reference voltage to be produced in the replica driver circuit. The voltage across capacitor CLOOP is equal to VGS+R*I. The voltage imparted across capacitor CISO is equal to VGS′+R/m*m*I′=VGS′+R*I′, identical to the former under ideal conditions. However, in presence of any DC differences due to ohmic drop, or transient thermal drift, or any other long-term differentiation between the ground voltage of the precision loop and reference driver VGND, versus the ground voltage of the replicated driver VGND′, the replicated reference voltage (and current) will be in error. It is apparent that the voltage VGS′+R*I′ will differ from the original VGS+R*I by an amount ΔV=VGND−VGND′. On the other hand, it is not desirable to tie VGND to VGND′, as this would modulate the Vref of the precision loop thus defeating the purpose of circuit 200. Device sizes W, M*W, current M*I, and replica voltage VREF′ are also shown in FIG. 3.
What is desired is a reference circuit that can provide a precision isolated reference voltage, but that is radiation tolerant and does not have the ground errors present in the prior art.